1. Field of the Invention
The present invention relates to a method for probing an integrated circuit (IC), and more particularly, to a method for placing probing pads in an integrated circuit (IC).
2. Description of the Related Art
During the research and fabrication of integrated circuits, IC debugging and failure analysis are performed on defective ICs. A general method is to probe a suspecious path inside the invalid IC. In order to probe a signal status of the path inside the IC, preparation must be taken before the probing operation.
First, before probing, a net corresponding to a layout is selected from a netlist. Then, an appropriate probing point is determined based on experience. Then, a FIB (focus ion beam) technique is applied in the probing point to drill a hole on a passivation layer and an inter-metal-dielectric layer (IMD). Finally, metal is deposited on the probing point to form a probing pad for probing.
However, this method has many disadvantages; for example, searching the appropriate probing point based on experience is very inefficient. In addition, the original circuitry may be altered due to the hole drilled by FIB technique and the probing pad formed by deposition. Whether the process of drilling the hole by FIB technique and forming probing pad by deposition are correct or not has not been verified yet. For example, a hole drilled close to another net will result in shortcut of two different nets. Therefore, it is hard to determine whether the probing result is a real signal status of the IC or is an incorrect signal status from the wrong process of drilling the hole by FIB technique and forming the probing pad by deposition.